Static random access memory (SRAM) is a type of volatile semiconductor memory that stores data bits using bistable circuitry that does not need refreshing. An SRAM cell may be referred to as a bit cell because it stores one bit of information, represented by the logic state of two cross coupled inverters. Memory arrays include multiple bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and to a reference voltage. Logic signals on bit lines control reading from and writing to a bit cell, with a word line controlling connections of the bit lines to the inverters, which otherwise float. A word line may be coupled to the bit cells in a row of a memory array, with different word lines provided for different rows.
A bit cell in an SRAM configuration known as six-transistor (6T) includes a pair of access transistors PG1 and PG2 switched by a signal on a word line WL and providing access to a pair of cross-coupled inverters, specifically by coupling signals on bit lines to complementary nodes of the cross-coupled inverters during read and write operations. “PG” in PG1 and PG2 may stand for “passing gate” because those transistors pass signals on the bit lines to the nodes of the cross coupled inverters when the word line signal at the gate terminal of transistors PG1 and PG2 becomes true (typically logical high on the gates of NMOS FETs). During standby mode, word line WL is not asserted (logical low), and the access transistors PG1 and PG2 disconnect the bit cell from the bit lines. The cross-coupled inverters are coupled to the power supply and reinforce each other to maintain one of two possible logic states with a stored data bit represented by the voltage at one of the nodes of the inverters and the complement of that bit at an other node of the inverters. It is an understood convention that while complementary data values are stored at each of these nodes, the bit stored at one of the nodes is referred to as the bit value stored at the bit cell.
For a read operation, both bit lines of a bit cell are precharged high, and the word line WL is asserted. The stored data bit at one of the nodes (the node that stores the data bit of the bit cell, per the above-mentioned convention) is transferred to one of the bit lines BL, and the data bit at the other node is transferred to the other bit line BLB (which stands for “bit line bar”, or bit line complement). A sense amplifier discerns which of BL and BLB is higher and which is lower, thereby determining the logic value stored in the bit cell. For a write operation, the value to be written is provided at BL, and the complement of that value is provided at BLB, when the word line WL is asserted.
During a read operation (read cycle), the correct (intended) functionality is that the data at the storage nodes in a bit cell remains unchanged while being read. But in some instances the storage nodes may undesirably interchange (swap) logic values, causing the bit cell to flip from one logic state to the other. Such an undesirable occurrence may be referred to as a “read flip” and may be due to various factors, e.g., storage device mismatch (e.g., imbalance in the strengths of transistors that form the bit cell) or a large amount of charge rushing into a storage node when a word line is asserted, thereby overwhelming the device. Read flips introduce errors in the data stored in the SRAM.
A known approach for addressing the issue of read flips is to reduce the constant level at which the word line is asserted. This approach is referred to as “under-drive” because the word line is driven at a lower level than when it is normally driven (i.e., WL is driven at a voltage level less than its normal level). For example, if the word line is ordinarily driven at a constant voltage of 5 V throughout a read or write cycle, the under-drive scenario may involve driving the word line at a constant level of 4 V (or some other constant fraction of 5 V) throughout the cycle. Under-driving the word line may reduce or eliminate the occurrence of read flips, by improving the static noise margin for read operations, but the under-drive approach has its own disadvantages. First, asserting WL at a reduced level (e.g., 4 V instead of 5 V) slows down the read operation, as it takes longer for a bit line BL to acquire its final value that corresponds to the value stored in the bit cell. Second, under-drive may reduce the occurrence of read flips at the expense of undesired functionality during write cycles, namely, increasing the probability of failure to write an opposite value successfully into the bit cell when attempted. If the bit cell originally stores a value of ‘1’, an attempt to write a ‘0’ into the bit cell (i.e., to swap the values stored at the storage nodes) may be unsuccessful because of a write margin issue introduced by the under-driven word line. In other words, the benefit of avoiding undesired read flips by using the word line under-drive approach comes at the cost of failing to perform desired “write flips.”
The power supply voltage to the bit cell is also pertinent. The lowest VDD voltage (positive power supply voltage) at which an SRAM bit cell may function is referred to as Vccmin. Having a low cell VDD near Vccmin reduces leakage current and also reduces the incidence of read flips. Having a high cell VDD improves the probability of successful write operations. By choosing a voltage for the constant WL under-drive level, one may seek a balance (tradeoff) between the read Vccmin and the write Vccmin, but what is needed is a solution for improving both the read Vccmin and the write Vccmin.